1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, it relates to the structure of a semiconductor memory device suitable for fabrication of a system device combining a memory circuit and a logic circuit.
2. Description of the Prior Art
In recent years, a system requiring parallel processing of mass data such as video data processing is increasingly employed.
Such a system employs a synchronous DRAM (hereinafter referred to as SDRAM) operating in synchronization with a clock signal for implementing quick access to a dynamic random access memory (hereinafter referred to as DRAM) or the like employed as a main memory following improvement in operating speed of a microprocessor (hereinafter referred to as MPU).
Such an SDRAM or the like employs a bank structure splitting a memory cell array into banks capable of operating independently of each other, in order to enable operations at a higher speed. In other words, the operations of each bank are independently controlled as to a row-system operation and a column-system operation. Quicker access is implemented by interleave-operating such banks and reducing a precharge time or the like.
In recent years, however, a DRAM/logic circuit hybrid chip, for example, has been developed by integrating a memory circuit and a logic circuit on a single chip, in order to attain a more advanced multi-function structure, improvement of the data processing speed and the like. In this case, the width of a data bus (the number of bits of simultaneously transferred data) transferring data between the memory circuit such as a DRAM and the logic circuit integrated on the single chip tends to increase for performing high-speed processing.
While high-speed processing can be implemented by increasing the width of an internal data bus on the chip, flexible manufacturing may be required depending on the system. In this case, the aforementioned structure of the DRAM/logic circuit hybrid chip results in the following problem:
The memory capacity required to the memory circuit and the word structure (the bit number of one word or the like) for transmitting/receiving data to/from the logic circuit vary with the performance required to the system or the like. If designing the circuits on the single chip for each system in response to the specifications when fabricating such a semiconductor device, therefore, a long term is disadvantageously required for product development.
In order to solve this problem, Japanese Patent Laying-Open No. 10-111864 (1998), for example, discloses a technique of connecting a RAM board and an MPU board serving as LSI cores oppositely to each other through a bonding technique for a semiconductor chip thereby fabricating a system formed by a logic circuit and a memory circuit as an integral device, in order to reduce the term for developing a semiconductor integrated circuit device while improving the performance of the circuits and reducing the cost.
In this technique, however, pads for attaining electrical connection must be formed on each of the boards oppositely bonded to each other with correct registration, leading to limitation in degree of freedom in circuit design of both the RAM board and the MPU board.
On the other hand, input/output lines (pairs of I/O lines) reading data from memory cells and transmitting the read data to an interface circuit are generally layered in view of improvement of the operating speed or the like. In order to transmit data read from a memory cell through any of the layered pairs of I/O lines, a gate circuit is provided for selectively connecting a pair of bit lines connected with the memory cell selected in reading with the pair of I/O lines transmitting the data. The number of elements of such a gate circuit tends to increase in a multi-bank memory cell array.
In order to input/output data with the aforementioned large data bus width, in particular, it is necessary to increase the number of pairs of I/O lines capable of operating independently of each other, leading to increase of the number of the aforementioned gate circuits and the number of elements forming the same.
An object of the present invention is, in relation to a system including a memory circuit and a logic circuit structured with an integrated circuit device formed on a semiconductor substrate, to provide a semiconductor memory device capable of reducing the term for development thereof.
Another object of the present invention is to provide a semiconductor memory device capable of efficiently transmitting/receiving data to/from a logic circuit with a large data bus width.
Still another object of the present invention is to provide a semiconductor memory device enabling data transmission/receiving to/from a logic circuit with a large data bus width as well as improvement in efficiency of redundancy repair.
Briefly stated, the present invention is directed to a memory circuit/logic circuit integrated device comprising a logic circuit chip, a memory chip and a plurality of connect members.
The logic circuit chip is formed on a first major surface of a first semiconductor substrate. The logic circuit chip includes a plurality of first input/output pads for electrically interfacing with an external device.
The memory chip is separated to include at least one memory circuit among a plurality of memory circuits formed on a second major surface of a second semiconductor substrate to have separable spaces.
The memory chip includes an insulator layer provided on the outermost surface and an interface wiring layer providable immediately under the insulator layer in common for a plurality of memory circuits among the memory circuits.
The interface wiring layer has a plurality of second input/output pad parts provided on a position corresponding to an opening part of the insulator layer for electrically interfacing with the external device.
The plurality of connect members connect the plurality of first input/output pads and the corresponding second input/output pad parts respectively while opposing the first major surface of the logic circuit chip and the second major surface of the memory chip to each other.
According to another aspect of the present invention, a memory circuit/logic circuit integrated device comprises a logic circuit chip, a memory chip and a plurality of connect members.
The logic circuit chip is formed on a first major surface of a first semiconductor substrate. The logic circuit chip includes a plurality of first input/output pads for electrically interfacing with an external device.
The memory chip is integrally separated from a plurality of memory circuits formed on a second major surface of a second semiconductor device to have separable spaces, and includes at least two memory circuits.
The memory chip includes an insulator layer provided on the outermost surface and an interface wiring layer provided immediately under the insulator layer in common for the memory circuits.
The interface wiring layer has a wiring part connecting an input/output node of each of the memory circuits and a plurality of second input/output pad parts provided on a position corresponding to an opening part of the insulator layer for electrically interfacing with the external device.
The plurality of connect members connect the plurality of first input/output pads and the corresponding second input/output pad parts respectively while opposing the first major surface of the logic circuit chip and the second major surface of the memory chip to each other.
Preferably, each of the memory circuits includes a memory cell array having a plurality of memory cells arranged in rows and columns, a plurality of word lines arranged along the row direction of the memory cell array, a row selection circuit provided in correspondence to the memory cell array for selectively activating the word lines in response to an address signal, a plurality of pairs of bit lines provided in correspondence to the memory cell columns of the memory cell array, a plurality of pairs of data lines provided for a first plurality of pairs of bit lines for transmitting/receiving data to/from a selected memory cell, and a plurality of selection circuits selectively enabling data transmission between the pairs of data lines and the corresponding first plurality of pairs of bit lines.
More preferably, the memory circuit/logic circuit integrated device further comprises a redundancy memory cell row provided on an end portion of the memory cell array, and the redundancy memory cell row has latch circuits of a number corresponding to the memory cell columns for holding stored data.
Accordingly, a principal advantage of the present invention resides in that the term for designing the memory circuit and the fabrication steps therefor as well as the term for developing the memory circuit/logic circuit integrated device can be reduced.
Another advantage of the present invention resides in that a plurality of memory cell columns can share a data input/output structure and hence a structure transmitting/receiving data to/from the logic circuit with a large data bus width can be efficiently implemented.
Still another advantage of the present invention resides in that a redundancy memory cell in a redundancy memory cell block provided independently of the memory cell array replaces a faulty memory cell, whereby the efficiency of redundancy replacement can be improved.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.